Multi-tier KV cache system targets GPU inference memory bottlenecks

Key-value cache memory management is the main bottleneck for throughput and cost in large-scale GPU inference serving, according to an arXiv preprint. The author cites three problems: missing unified cache sizing across attention designs, especially multi-head latent attention unsupported in general frameworks and linked to up to 57 times memory over-provisioning; confining the cache to GPU high-bandwidth memory despite CPU DRAM, CXL memory, NVMe via GPUDirect Storage, RDMA, and parallel filesystems; and reactive eviction that discards reusable state and forces recomputation. The proposed system combines architecture-aware sizing, a six-tier memory hierarchy, and a Bayesian reuse predictor. Exact sizing per attention type yields a 7.4 times batch-size gain for the one multi-head latent attention model evaluated, DeepSeek-V3, while three grouped-query attention models see 1.0 times, 1.0 times, and 0.7 times, so the grouped-query benefit is fleet-wide unified sizing rather than larger per-model batches. The hierarchy extends effective cache capacity from 40 gigabytes to more than 38 terabytes per node while keeping sub-millisecond time-to-first-token for hot entries. A Bayesian reuse predictor with Beta conjugate priors over 16 block-type and transition-type pairs drives exponential-moving-average head-granular eviction and RoPE-aware prefetching. Component validation on ShareGPT, LMSYS-Chat-1M, and agentic trace replay shows 70 to 84 percent cache hit rates. Analytical projections that combine those components with published hardware specs point to 1.4 to 2.1 times lower time-to-first-token, 1.7 to 2.9 times higher throughput, and 47 percent lower cost versus published baselines; the paper labels those cluster-scale figures as analytical and without error bars.